::[PDP-11]::

The first PDP-11 was introduced in 1970 as the model 20 (PDP11/20). It introduced several features that weren't common at the time for minicomputers:-
* Multiple registers (8)
* Multiple addressing modes (8 and another 4 if the PC is used)
* Word (16 bit) and byte (8) address modes
* Hardware stack
* Processor error traps
* Vectored interrupts
* Multiple interrupt levels (4)
* Unified bus for memory and peripherals (Unibus)
* Memory mapped I/O registers

The instruction set was extensively modelled and described in ISP (Instruction Set Processor) notation before the hardware was designed. The 11/20 instructions (now called the base instruction set) was largely orthogonal, in that the memory reference instructions could all use the same addressing modes. By treating I/O controller registers as memory locations, no special I/O instructions were needed, since normal memory reference modes would do.
The CPU had eight registers, six general purpose, the stack pointer (sp or r6) and the program counter (pc or r7). By having the program counter and stack pointer as part of the general register set, no special instructions were required to use the stack and the program counter was available to extend addressing modes. A jump to location 0 could be implemented as either "jmp 0" or "clr pc".
Each I/O device has its own trap vector, and an interrupt would save the current program counter (PC) and processor status word (PSW) on the stack and fetch new ones from the trap vector. Since the new PSW could set a new interrupt priority, there was no need to set mask registers to disable lower priority interrupts.
Processor traps were treated in a similar way, and the machine could detect non-existent memory references (or I/O registers), unimplemented instructions, unaligned memory access, stack overflows and power failure.
The early machines had a 'programmers console' of switches and lights (11/20 and 11/45 were incandescent and frequently failed ). The machines could be halted, single stepped and memory locations inspected or altered. The CPU register set were mapped to locations 0177700-01777007 and beyond for internal state registers. The 11/45 had special register deposit/examine switches. Latter machines and all the LSI based ones had 'console' emulators that used the console serial port to replace the switch functions with ASCII commands.
A typical early PDP11/20 system might consist of the CPU, 8 or 16 Kbytes of core memory, a ASR-33 teletype as console and a high-speed reader/punch.
The PDP11/20 was the only '11' not to have a microcoded processor, suitable ROMS were unavailable at the time. The 'core' memory was comparatively slow at 1.2us for a read/write cycle. Within two years, the new PDP11/45 was introduced which corrected several deficiencies, including the lack of hardware multiply, divide or multiple shift instructions, a limited address space (56Kb) and no floating point instructions. .

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